Novel Heterogeneous Integration Technology of III–V Layers and InGaAs FinFETs to Silicon

wileyonlinelibrary.com recent rich advancements in strain engineering, [ 2 ] metal gate stack with high-k dielectrics, [ 3 ] and transistor architecture, [ 4 ] up to the development of Si FinFET devices adopted in current CMOS technology. It is expected that downscaling of Si-based technology will eventually reach its physical limits below 10 nm technology node, a bottleneck that research now tries to overcome by replacing the channel material. A potential approach is to combine the advantages of III–V FET technology with the well-established Si CMOS platform. [ 5 ]